1. Technical Field
The present disclosure relates to a driving method for obtaining a linear gain variation of a transconductance amplifier.
The disclosure further relates to a driving circuit for a transconductance amplifier of the type comprising at least one transistor differential cell and the following description is made with reference to the field of application only for simplifying the description thereof.
2. Description of the Related Art
As is well known, transconductance amplifiers are widely used to drive current, and are devices capable of receiving an input voltage and providing an output current substantially proportional to the received input voltage.
A transconductance amplifier typically comprises a differential pair, in particular of bipolar or field effect transistors (JFET, MOSFET), with mirror load and suitably biased.
A simplified diagram of a transconductance amplifier is shown in FIG. 1, globally indicated with reference numeral 1.
In particular, the amplifier 1 comprises a first T1 and a second transistor T2, in the example bipolar transistors, inserted between a mirror load block 2, in turn connected to a first voltage reference, in particular a positive supply VDD, and a biasing block 3, in turn connected to a second voltage reference, in particular a negative supply VSS.
More in particular, the first bipolar transistor T1 is inserted between a first mirror circuit node XS1 and a first degenerative circuit node XD1 and has a control terminal, or base, connected to an input terminal IN, whereas the second bipolar transistor T2 is inserted between a second mirror circuit node XS2 and a second degenerative circuit node XD2 and has a control terminal, or base, connected to a further voltage reference, in particular a ground GND, the second mirror circuit node XS2 being further connected to an output terminal OUT of the amplifier 1.
Moreover, the mirror load block 2 comprises a first mirror transistor MS1 inserted between the first positive supply voltage reference VDD and the first mirror circuit node XS1 and having a control terminal, or gate, diode-connected to the first mirror circuit node XS1 as well as to a control terminal, or gate, of a second mirror transistor MS2 inserted between the first positive supply voltage reference VDD and the second mirror circuit node XS2, that is, to the output terminal OUT of the amplifier 1.
Moreover, the biasing block 3 comprises a first biasing transistor MB1 inserted between the first degenerative circuit node XD1 and the second negative supply voltage reference VSS and having a control terminal, or gate, connected to a biasing terminal XB from which it receives a biasing voltage Vbias. The biasing block further includes a second biasing transistor MB2 inserted between the second degenerative circuit node XD2 and the second negative supply voltage reference VSS and having a control terminal, or gate, coupled to the gate of the first biasing transistor MB1. This biasing voltage Vbias imposes a desired current that flows in the biasing transistors, MB1 and MB2, and which depends on the type of application the amplifier 1 is intended for.
The amplifier 1 further comprises a degenerative resistance Rdeg inserted between the first and second degenerative circuit nodes, XD1 and XD2, as well as a degenerative driving transistor MD, inserted in parallel with the degenerative resistance Rdeg, between the first and second degenerative circuit nodes, XD1 and XD2, and having a control terminal, or gate, connected to a gate driving terminal XG and therefrom receiving a gate driving voltage Vtgc.
In particular, the degenerative driving transistor MD allows modifying the equivalent resistance or degenerative resistance of the amplifier 1 and varying the transconductance gain accordingly.
More in detail, when the degenerative driving transistor MD is powered, its resistance value Ron dominates relative to the degenerative resistance Rdeg, which is parallel thereto. In particular, the switch on resistance value Ron of the driving transistor MD is usually equal to 1/100 of the value of the degenerative resistance Rdeg, the parallel connection thereof allowing to obtain a high transconductance gain for the amplifier 1 when the degenerative driving transistor MD is switched on. On the other hand, when the degenerative driving transistor MD is switched off, the degenerative resistance Rdeg dominates and establishes the transconductance gain of the amplifier 1.
However, while the amplifier structure as illustrated in FIG. 1 is controlled by the gate driving voltage Vtgc, which modifies the degenerative resistance thereof by modifying the equivalent resistance of the degenerative driving transistor MD, it exhibits a highly non-linear link between this gate driving voltage Vtgc and the transconductance gain gm of the amplifier 1. In fact, moving the gate driving voltage Vtgc linearly, the equivalent resistance of the degenerative driving transistor MD varies in a non-linear manner, and therefore there is an overall non-linear variation of the transconductance gain of the amplifier 1.